Cypress Adopts Cadence Digital Implementation and Circuit Simulation Tools
Cadence Design Systems announced that after an extensive competitive evaluation, Cypress Semiconductor selected the full Cadence RTL-to-signoff digital design flow and complete Spectre circuit simulation platform for all of its 40nm automotive chip designs. The evaluation process showed Cypress the opportunity to dramatically improve its turnaround time and productivity with the Cadence solution when compared with its previous flow.
The Cadence digital flow consists of the Innovus Implementation System, the Genus Synthesis Solution, the Tempus Timing Signoff Solution, Conformal Low Power and the Quantus QRC Extraction Solution. These tools collectively enabled Cypress to achieve improved individual tool throughput and productivity gains. Specifically, the Innovus Implementation System provided Cypress with significant power, performance and area (PPA) benefits.
In particular, low power was a critical requirement for the Cypress 40nm automotive designs. Cypress develops complex designs with multiple power domains that require comprehensive UPF constraints and many timing modes and corners. The Cadence low-power flow offers IEEE 1801 support, and provided Cypress with area and power reductions.
The Spectre circuit simulation platform, including the Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and Spectre RF Option, can provide Cypress with improved accuracy, speed and ease of use. The initial Spectre XPS next-generation FastSpice simulator evaluation yielded up to 10X turnaround time improvement over Cypress’s previous Cadence flow.
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