It has been announced by Cadence Design Systems, that Innovium has adopted the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform to achieve first-pass silicon success on its high-performance, scalable, production-ready TERALYNX Ethernet switch for the data center.
Using both the Palladium Z1 and Protium S1 platforms, Innovium was able to expedite verification closure and attain rapid bring-up of its software stack, thereby significantly accelerating development of its Ethernet switch.
Innovium adopted the Palladium Z1 and Protium S1 platforms because of the common, congruent flow the platforms provide and their ability to perform early software development. Due to the common flow, Innovium’s engineers were able to reuse significant portions of their verification environment, which improved productivity and reduced overall time to market.
The Palladium Z1 emulation platform enabled Innovium to validate its architecture, perform chip verification and tune performance early in the verification process. Using the Protium S1 prototyping platform, Innovium was able to quickly and effectively complete early software development of its Ethernet switch, while also completing hardware and software performance testing. When compared to simulation, Innovium saw a 3,000 times speedup with the Palladium Z1 platform and a 6,000 times speedup using the Protium S1 platform.
Avinash Mani, VP of Engineering at Innovium, said: “With the Palladium Z1 and Protium S1 platforms, we were able to efficiently balance emulation for chip verification and architecture validation in conjunction with prototyping for early software development and performance testing.
“The platforms’ common flow allowed us to achieve fast migration between emulation and prototyping, enabling us to accelerate development for TERALYNX, our highly innovative production-ready 2T to 12.8Tbps data center switch family that offers unmatched performance, telemetry and low latency.”
The Palladium Z1 Enterprise Emulation Platform and Protium S1 FPGA-Based Prototyping Platform are part of the Cadence Verification Suite. The Verification Suite is comprised of core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.
The Verification Suite supports the Cadence System Design Enablement strategy, which enables systems and semiconductor companies to create complete, differentiated end products more efficiently.