Engineering 101

IC Validator Delivers Superior Performance for DRC and LVS Signoff

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Synopsys has announced that The MOSIS Service has selected Synopsys’ IC Validator tool for physical verification signoff. IC Validator’s feature-rich physical verification solution, coupled with a highly scalable engine, has allowed The MOSIS Service to achieve significantly faster physical signoff.

The MOSIS Service deployed IC Validator for full-chip design rule checking (DRC) and layout-versus-schematic (LVS) signoff on designs in FinFET process technologies.

“The MOSIS Service processes designs for a high volume of multi-project wafers that speed production and reduce costs for our customers. We require a highly productive physical verification solution to ensure on-time delivery of design tapeouts,” said James Whalen, Co-Director of The MOSIS Service. “IC Validator has enabled our engineers with productivity and performance functionality to sign off designs on-time.”

IC Validator, a key component of Synopsys’ Fusion Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (PERC), dummy metal fill, and design-for-manufacturability (DFM) enhancement capabilities.

IC Validator is architected for high performance and scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than a thousand CPUs.

“At advanced process technologies, physical verification closure within schedule has become a challenge because of the increasing manufacturing complexity,” said Dan Page, Vice President, Design Group at Synopsys. “Through high performance, scalability, and readily available optimized runsets from all major foundries, IC Validator is providing designers with the fastest path to production silicon.”

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