NASA’s Jet Propulsion Laboratory in Southern California has selected Microchip Technology to develop a High-Performance Spaceflight Computing (HPSC) processor that will provide at least 100 times the computational capacity of current spaceflight computers. This capability will advance various future space missions, from planetary exploration to lunar and Mars surface missions.
Microchip will architect, design, and deliver the HPSC processor over the next three years, with the goal of employing the processor on future lunar and planetary exploration missions. Microchip’s processor architecture will significantly improve the overall computing efficiency for these missions by enabling computing power to be scalable, based on mission needs.
The design will also be more reliable and have a higher fault tolerance. The processor will enable spacecraft computers to perform calculations up to 100 times faster than today’s state-of-the-art space computers. As part of NASA’s ongoing commercial partnership efforts, the work will take place under a $50 million firm-fixed-price contract, with Microchip contributing significant research and development costs to complete the project.
Current space-qualified computing technology is designed to address the most computationally-intensive part of a mission – a practice that leads to overdesigning and inefficient use of computing power. For example, a Mars surface mission demands high-speed data movement and intense calculation during the planetary landing sequence. However, routine mobility and science operations require fewer calculations and tasks per second. Microchip’s new processor architecture offers the flexibility for the processing power to ebb and flow depending on current operational requirements. Certain processing functions can also be turned off when not in use, reducing power consumption. This capability will save a large amount of energy and improve overall computing efficiency for space missions.