Engineering 101

Synopsys and Socionext Expand Collaboration to Deploy HBM2E IP

Synopsys and Socionext have announced their collaboration to expand Socionext’s use of Synopsys’ broad DesignWare IP to include Synopsys’ HBM2E IP for maximum memory throughput in AI and high-performance computing (HPC) applications.

Socionext selected Synopsys’ HBM2E IP, operating at 3.6 Gbps, to meet the stringent capacity, power, and compute performance requirements of its innovative AI engine and accelerator system-on-chip (SoC). The Synopsys IP provides efficient heterogeneous integration with the shortest 2.5D interposer package routes.

“As a global leader in SoC solutions with differentiated functionalities, we face very tight delivery deadlines,” said Yutaka Hayashi, Vice President of Automotive & Industrial Business Group at Socionext. “By leveraging Synopsys’ DesignWare HBM2E IP and integrated full-system multi-die design platform, Socionext can deliver world-class high-performance, high-capacity and power-efficient SoCs on the five-nanometer FinFET process to the market. We are also collaborating with Synopsys on using their next-generation DesignWare IP solutions including HBM3.”

With an aggregated bandwidth of 460 gigabytes per second, the DesignWare HBM2E PHY IP delivers the required massive compute performance of SoCs in advanced FinFET processes. The HBM2E IP is part of Synopsys’ comprehensive memory interface IP solution that includes DDR5/4/3/2 and LPDDR5/4//4X/3/2 IP, which have been validated in hundreds of designs and shipped in millions of SoCs.

“As the leading memory interface IP provider, Synopsys provides innovative companies, like Socionext, with a highly competitive HBM2/2E IP solution that addresses the aggressive power and memory bandwidth requirements of advanced high-performance computing SoCs,” added John Koeter, Senior Vice President of Marketing and Strategy for IP at Synopsys. “Synopsys’ silicon-proven DesignWare HBM2/2E IP, with over 25 design wins and customers in volume production, enables designers to confidently integrate the IP into their SoCs with less risk and achieve a faster path to silicon success.”

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