Engineering 101

CEVA declared winner of CEM 2017 Editor’s Choice Awards

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CEVA has announced that it has been declared a winner in the China Electronic Market (CEM) 2017 Editor’s Choice Awards. The award recognizes the CEVA-X1 IoT Processor as ‘The most competitive MCU and DSP product in China’.

The CEVA-X1 IoT processor implements a single-core DSP+CPU architecture, specifically designed to address the severe size, power and cost constraints imposed by the latest eMTC Cat-M1 and eNB-IoT Cat-NB2 standards, as well as future FeMTC and 5G cellular IoT deployments.

“We are delighted to accept this prestigious award for our CEVA-X1 IoT processor, particularly at a time when cellular IoT services are being launched around the world,” said Michael Boukaya, vice president and general manager of the wireless business unit at CEVA.

“NB-IoT is set to connect billions of IoT devices to the cellular networks in the coming years. Our CEVA-X1 processor is at the core of our DragonFly NB1 platform that vastly simplifies our customers development of NB-IoT chips for a wide range of applications, including the smart home, smart utilities, asset tracking, and security, as well as environmental, industrial and agricultural monitoring and control.”

The CEVA-Dragonfly NB1 pre-integrates together the CEVA-X1 processor, an optimized RF, a baseband, and a protocol software to offer a complete Release 14 Cat-NB2 modem IP solution that reduces time-to-market and lowers entry barriers. The CEVA-X1 in the system can also serve as a multi-purpose, multi-mode processing hub for a range of tightly-associated IoT workloads, including WiFi 802.11n, 802.11ac, Bluetooth/BLE, ZigBee/Thread, LoRa, SIGFOX, narrowband voice, GNSS and sensor fusion. Crucially, the CEVA-X1 can handle multiple processing workloads simultaneously, allowing developers complete flexibility in tailoring their systems to meet the requirements of any IoT use case.

Derived from the NEW CEVA-X architecture framework, the CEVA-X1 employs an extended Instruction Set Architecture (ISA) that, in addition to DSP processing, also allows it to efficiently handle CPU software workloads, such as protocol stacks and system control.

Source CEVA

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