High-performance timing company Pearl Semiconductor unveiled an all-digital phase-locked loop PLL technology for ultra-low-noise timing solutions. The “SpurFree” architecture targets timing solutions to address increased data flow within/between data centers, including optical transmission networks and 5G backhaul.
Engineers designed SpurFree to solve the fractional “spurs” created by PLLs—electronic noise that causes signal interference. The technology is validated in silicon, yielding a programmable any-rate reference clock with sub-75 femtosecond performance, with frequencies up to 3GHz, competing with best-in-class timing products on the market today. Product applications include a range of programmable reference clocks, multi-output clock generators, clock buffers, jitter attenuators, and network synchronizers.
Today’s high-frequency, low-noise reference clocks use bulky quartz SAW devices that lack programmability. There is intense pressure on all timing product providers to develop new technologies that meet existing noise and programmability requirements.
Pearl will demonstrate its technology at Electronica 2022 in Hall C2, Booth 565, from Nov 15th to Nov 18th in Munich, Germany.