Compute Express Link is changing how servers access and share memory. New controllers from Marvell show how memory expansion, compression and resource pooling are becoming part of AI infrastructure design.
The processor gets most of the attention in discussions about AI performance. More cores, faster accelerators and increasingly powerful GPUs dominate the conversation about what the next generation of computing hardware will accomplish.
But processing power has limited value when the system cannot supply enough data to keep it busy.
For many AI workloads, memory capacity and bandwidth have become major constraints. Large models require substantial memory to hold their parameters and intermediate data. Applications involving long context windows or multiple simultaneous users place additional demands on the system.
Adding more processing hardware does not automatically solve those problems.
Engineers must also determine where data is stored, how quickly processors access it and whether memory resources are being used efficiently.
Compute Express Link, or CXL, offers another approach to those challenges by extending the relationship between processors and memory beyond conventional directly attached configurations.
Why Memory Has Become a Limiting Factor
Traditional server architectures connect processors to memory through dedicated memory controllers and channels.
This arrangement provides predictable access to local DRAM, but the available capacity is constrained by the processor’s supported memory configuration and the physical slots available in the system.
Increasing capacity often means installing higher-density memory modules or adding servers.
Neither option necessarily makes efficient use of the memory already installed throughout a data center.
One server might have substantial unused capacity while another struggles to accommodate a demanding workload. In conventional configurations, the second server cannot simply borrow the first server’s local DRAM.
AI inference makes these limitations particularly noticeable.
During inference, large language models generate and maintain intermediate information used to process incoming requests and produce responses.
The key-value cache, commonly called the KV cache, stores information associated with previous tokens so the model does not need to recompute everything for each subsequent token.
As context windows grow, KV-cache requirements increase. Serving multiple users simultaneously adds further pressure.
Insufficient memory capacity can force systems to reduce concurrency, move data between memory tiers or use less efficient configurations.
Memory bandwidth also matters. Even when enough capacity exists, slow data movement can leave processors waiting.
The result is a system in which adding more compute resources produces diminishing returns unless memory architecture improves alongside them.
What CXL Changes
CXL is a cache-coherent interconnect built on PCI Express infrastructure.
It enables compatible processors and devices to exchange data while supporting memory-oriented operations and coherency mechanisms.
One important application is memory expansion.
Instead of relying exclusively on DRAM connected directly to a processor’s memory channels, a server can access additional memory through a CXL-compatible device.
A memory expansion controller manages the connection between the host system and the external DRAM.
This provides another way to increase available memory capacity without requiring all memory to occupy the processor’s native DIMM slots.
CXL also supports more flexible approaches to memory sharing.
In suitable configurations, memory resources can be organized into pools accessible by multiple hosts. Software and system management determine how those resources are assigned and used.
This opens the possibility of allocating memory according to workload requirements rather than permanently tying every installed module to one server.
There are trade-offs.
CXL-attached memory introduces different latency and bandwidth characteristics from locally attached DRAM. Applications must be evaluated to determine which data benefits from remaining close to the processor and which data can tolerate placement in another memory tier.
The technology is therefore better understood as an additional memory architecture option than a direct replacement for conventional DRAM connections.
More Memory Behind a Single Controller
Marvell’s second-generation Structera X controllers provide a recent example of how CXL memory expansion is developing.
Introduced in October 2026, the Structera X 3406 and 3506 support CXL 3.2 and PCIe Gen 6 connectivity.
Both devices offer six memory channels, an increase from four in Marvell’s previous generation.
The Structera X 3406 supports DDR4 memory, with configurations reaching 18 RDIMMs and up to 9TB of capacity per controller.
The Structera X 3506 supports DDR5, with up to 12 DIMMs and 6TB per controller.
The devices support connections to as many as four hosts and provide up to 256GB/s of host bandwidth.
These capabilities are particularly relevant to data centers managing large memory footprints across multiple compute nodes.
The DDR4 controller also presents an opportunity to reuse existing memory modules as operators transition newer servers to DDR5.
Rather than discarding functioning DDR4 resources, operators could potentially redeploy them in CXL expansion configurations where their performance characteristics remain suitable.
This does not eliminate the need to evaluate memory latency, power consumption or system compatibility. It does, however, introduce another option for managing installed memory resources.
Compression Adds Another Layer
Physical memory capacity is not the only way to increase the amount of data a system holds.
Memory compression stores data in a reduced representation, allowing more information to occupy the same amount of physical DRAM when the data is sufficiently compressible.
Marvell’s Structera X controllers incorporate inline LZ4 compression and decompression.
The company reports up to 250GB/s of compression and decompression throughput in its latest generation, with effective memory-capacity gains of two to three times for suitable workloads.
Those gains are workload-dependent. Some data compresses substantially, while other data offers limited opportunity for reduction.
Compression also introduces processing and latency considerations. The controller must perform the additional operations quickly enough to avoid becoming a bottleneck.
For AI workloads with large memory requirements, however, compression offers another method of increasing usable capacity without a corresponding increase in installed DRAM.
It also illustrates how memory expansion controllers are evolving beyond relatively simple interfaces.
They increasingly incorporate data-management, security and reliability functions that influence overall system performance.
Sharing Memory Without Losing Control
Memory pooling introduces additional system-design questions.
If multiple hosts access a shared pool, the infrastructure needs mechanisms for resource allocation, isolation, error handling and protection of data moving between devices.
A failure in a shared memory resource could affect more than one host. Likewise, improper isolation could create security concerns in multi-tenant environments.
These issues make reliability, availability and serviceability important considerations for CXL deployments.
Modern controllers incorporate error correction, memory protection and security capabilities to address parts of the problem.
But hardware features alone do not determine whether memory pooling works effectively.
Operating systems, firmware, hypervisors and orchestration software must understand the available resources and assign them appropriately.
Application behavior matters as well.
A workload with frequent latency-sensitive memory accesses might perform better with local DRAM, while another application could benefit substantially from expanded capacity even with somewhat higher access latency.
The challenge is matching the memory tier to the workload rather than treating every gigabyte as interchangeable.
What Comes Next for Server Memory
CXL memory expansion is moving from early implementations toward broader integration into data-center architectures.
Marvell’s first-generation Structera X controllers are already shipping to hyperscale customers. The company expects the new 3406 and 3506 devices to begin sampling in the first quarter of 2027.
Their introduction reflects a larger change in how engineers approach computing infrastructure.
For years, server upgrades were largely discussed in terms of faster processors, more memory and higher-speed connections.
Those elements remain important, but the relationships between them are becoming more flexible.
Memory can be expanded through external controllers, shared across compatible hosts and compressed to improve effective capacity.
None of these approaches removes the physical limits of DRAM or the performance penalties associated with moving data. They do give architects more ways to manage those constraints.
As AI systems continue to grow, the ability to place data in the right memory resource may prove as important as the speed of the processor using it.
