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AnalogAI Taps Microchip’s memBrain Technology for Edge AI Processors That Learn on the Job

A robot navigating an unfamiliar environment or a drone encountering unexpected conditions needs to respond quickly. Most AI systems handle these situations using models trained beforehand, but adapting to new conditions often requires additional training resources.

AnalogAI is developing a different approach. The company has selected memBrain Synaptic Analog Generative Engine (SAGE) intellectual property from Microchip Technology’s Silicon Storage Technology (SST) subsidiary for its first edge AI processors.

The goal is to build processors capable of running AI models and training them simultaneously, allowing devices to adapt to changing environments without relying entirely on external computing resources.

AnalogAI is targeting applications such as humanoid robots, drones and autonomous vehicles, where power consumption and real-time responsiveness are important design considerations.

Bringing Training and Inference Together

Traditional AI development generally separates training from inference. Models are trained using substantial computing resources, then deployed to devices that use the trained models to make predictions or decisions.

AnalogAI’s approach combines the two operations at the edge.

Its processors will use a proprietary, hardware-aware algorithm designed to train and run inference simultaneously. This would allow an AI system to update its behavior as it encounters new conditions rather than relying exclusively on its initial training.

The company is using SST’s memBrain SAGE IP as the core inference engine for its first products, targeting analog compute-in-memory performance at or below one watt.

Keeping power consumption low is particularly important for battery-powered robots and drones, where additional computing hardware competes with motors, sensors and other systems for available energy.

Computing Where the Data Is Stored

The memBrain architecture uses analog compute-in-memory (aCIM), which performs computing operations within or near memory rather than repeatedly transferring data between separate memory and processing units.

Moving data consumes energy and introduces delays. Reducing this movement is one way to improve the efficiency of AI workloads, particularly those involving repeated mathematical operations.

SST’s memBrain SAGE IP is built on its SuperFlash nonvolatile memory technology.

At the center of the architecture is a tensor in-memory logic element, or TILE, incorporating a custom memory array, decoders and driver circuitry. Its optimized ESF3 memory cells store up to eight bits per cell and operate at nanoamp-level currents.

The IP also includes optimized digital-to-analog and analog-to-digital converters, summation circuitry, high-voltage bias circuitry and specialized test functions.

Together, these components provide the hardware needed to perform analog AI computations while maintaining low power consumption.

For AnalogAI, licensing an existing, silicon-proven architecture provides a starting point for developing its processors without designing the entire compute-in-memory subsystem from scratch.

A Path Toward Smaller Process Geometries

SST has already developed and deployed memBrain SAGE IP using 40 nm and 28 nm foundry processes. Development of a 22 nm version is included in its technology roadmap.

The architecture’s SuperFlash foundation provides nonvolatile storage, retaining information without continuous power.

AnalogAI selected the technology following an evaluation of available IP offerings, citing its combination of power efficiency, computing performance and development readiness.

The company has not announced specifications, pricing or a commercial availability date for its first processors.

For now, the agreement establishes the hardware foundation for AnalogAI’s edge AI platform. The larger technical objective is to move beyond processors that simply execute pretrained models and toward devices that continue learning as they operate, within the tight power budgets of embedded systems.

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