Engineering 101

Fastest Design Closure and Signoff for Process Nodes Delivered

Synopsys has announced that with its broad portfolio of golden signoff products, Synopsys has collaborated with Samsung Foundry to deliver a fully qualified flow with significant gains in accuracy, turnaround time and designer productivity.

By targeting 5G, artificial intelligence and high-performance computing SoCs, these gains enable customers at Samsung 5-nanometer (nm) to 3nm process nodes to achieve optimal power, performance, area (PPA) and accelerate time-to-results (TTR).

“Samsung Foundry serves many leading-edge customers in the most advanced application segments that demand the highest levels of design performance, robustness, and power efficiency,” said Sangyun Kim, Vice President of Foundry Design Technology at Samsung Electronics. “Our collaboration with Synopsys has been instrumental in delivering state-of-the-art signoff flows to our customers for our advanced 5 to 3nm process nodes.”

The Synopsys fully qualified signoff flow includes the following solutions:

  • PrimeTime: Supports ultra-low voltage variation, via variation and multi-input switching with three percent correlation to SPICE, 50% reduction in overall memory footprint and a twenty times performance increase for path-based analysis.
  • StarRC: Extraction with a two times runtime improvement and accuracy within one percent of golden reference.
  • StarRC Field Solver: Deployed as the golden reference for advanced node enablement.
  • PrimeECO: Enables five times faster design closure, eliminating costly iterations between implementation and signoff.
  • PrimePower: Provides an eight times faster gate-level power analysis using RTL simulation vectors.
  • SiliconSmart: Delivers ten times overall performance increase including enablement on Synopsys Cloud Service, significantly reducing the turnaround time for library characterization.

“Collaborations with industry leaders in semiconductor design and manufacturing is at the core of our continued innovations in design signoff,” said Jacob Avidan, senior vice president of engineering in Synopsys’ Design Group. “We are fortunate to team up with Samsung Foundry to drive these innovations across a wide range of signoff technologies pushing performance limits and reducing margins required for design with the highest degree of confidence on Samsung’s latest advanced process technologies. We look forward to continuing our collaboration for the next wave of designs and application segments.”

The collaboration spans the broad portfolio of Fusion Design Platform signoff solutions, including PrimeTime static timing analysis, PrimeECO design closure, PrimePower power analysis, StarRC extraction and SiliconSmart library characterization.

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