Cadence Design Systems has announced that Socionext used the Cadence full-flow digital and signoff tools for the successful production tapeout of its latest large, 16nm ASIC chip and has built a design environment for its 7nm designs. Using the capabilities of the integrated full flow, Socionext sped design closure on its 16nm design when compared with its previous solution.
The Socionext certified flow for the 16nm and 7nm designs includes the Cadence Genus Synthesis Solution, Cadence Conformal Equivalence Checker, Cadence Innovus Implementation System, Cadence Quantus Extraction Solution, Cadence Tempus Timing Signoff Solution, Cadence Voltus IC Power Integrity Solution, and Cadence Physical Verification System (PVS).
In particular, the Tempus Timing Signoff Solution enabled the Socionext team to meet design productivity goals for its 16nm production designs by using the Tempus SmartScope hierarchical models. The Tempus SmartScope models facilitate hierarchical static timing analysis (STA) signoff and signoff-accurate engineering change orders (ECOs) by letting users dynamically abstract portions of the design so they can analyse blocks with accurate chip-level context.
Additionally, the Voltus IC Power Integrity Solution enabled Socionext to reduce electromigration (EM) analysis turnaround time by 60 percent, which is critical for 16nm and below FinFET process technologies.
For Socionext’s 7nm design, the Innovus Implementation System’s Flex H-Tree capability in particular has already proven to be critical in enabling power, performance and area (PPA) benefits. The Flex H-Tree is an advanced clock synthesis technology that enables users to consider floorplan blockages and power tradeoffs, allowing Socionext to meet its target goal for clock skews.
Takuya Yasui, General Manager of LSI Development Division, Automotive & Industrial Business Group at Socionext, said: “As a leading ASIC and ASSP product supplier for various market segments, power, performance and area as well as overall turnaround time are incredibly important to us.
“We have successfully used the Cadence full-flow digital and signoff tools to deliver multiple chips at 16nm and have chosen the Cadence flow as our plan of record for both our 16nm and 7nm designs. Our close collaboration with Cadence was essential for our 16nm design success, and the Cadence full flow is now also an integral part of our development of future 7nm products.”
Dr Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence, added: “We recognise that the ASIC and ASSP market presents growing competitive requirements and design challenges, including added design complexity and shorter time-to-market demands. Cadence has collaborated with Socionext to successfully deploy the Cadence full-flow digital and signoff tools to help achieve design success. We look forward to continuing to support them with future designs.”
From synthesis through implementation and signoff, the Cadence integrated full-flow digital and signoff tools provide a fast path to design closure and better predictability. The digital and signoff full flow supports the company’s overall Intelligent System Design strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.