Engineering 101

Kit Enables Checking, Reporting, and Packaging of ASIC Designs

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It has been announced by Synopsys, that Faraday Technology Corporation, a leading fabless ASIC and IP provider, has adopted Synopsys’ SpyGlass Design Handoff Kit. Faraday has deployed the SpyGlass Design Handoff Kit to ensure ASIC designs meet design quality requirements before initiating ASIC design service and production.

The kit enables the required infrastructure for checking, reporting, and design packaging before handoff to the design service team. The software and methodologies needed to implement Faraday’s IP and system-on-chip (SoC) design qualification requirements will also be integrated into the SpyGlass Design Handoff Kit.

“We have worked closely with Synopsys to refine the process of validating the delivered quality of third-party silicon IP and SoC designs at the RTL level,” said Kun-Cheng Wu, Senior AVP of R&D at Faraday. “Faraday is using the SpyGlass Design Handoff Kit to guarantee design quality at handoff from IP providers and customers, reducing errors and iterations before ASIC production and accelerating time-to-market for our customers.”

Faraday requires IP providers and customers to validate their designs with the SpyGlass Design Handoff Kit to ensure a minimum level of completeness before handoff. SpyGlass, the industry-leading static solution, is the de facto tool for rule checking. The SpyGlass Design Handoff Kit is packaged with the necessary methodology and scripts to produce a design summary, dashboard, and datasheet detailing the fulfillment of all requirements.

“Starting with high-quality IP and design deliverables is a critical requirement for effective ASIC production,” said Sridhar Seshadri, Vice President of Engineering for the Verification Group at Synopsys. “We are confident in the ability of our SpyGlass product to improve the handoff of IP and ASIC designs between members of the semiconductor ecosystem.”

The SpyGlass Design Handoff Kit is available now.

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